1. Field of the Invention
The present invention relates to a method of fabricating a memory device. More particularly, the present invention relates to a method of fabricating a flash memory and floating gate.
2. Description of Related Art
Flash memory is a type of electrically erasable programmable read-only memory (EEPROM). Flash memory is a memory device that allows multiple data writing, reading and erasing operations. The stored data will be retained even after power to the device is removed. With these advantages, it has been broadly applied in personal computer and electronic equipment. In addition, the flash memory is also a type of high-speed non-volatile memory (NVM) that occupies very little space and consumes very little power. Moreover, erasing is carried out in a block-by-block fashion so that the operating speed is higher than most conventional memory devices.
A typical flash memory device has a floating gate and a control gate formed by doped polysilicon. The control gate is set up directly above the floating gate with an inter-gate dielectric layer separating the two. Furthermore, a tunneling oxide layer is also set between the floating gate and the underlying substrate (the so-called stacked gate flash memory). To operate the flash memory, a positive or negative voltage is applied to the control gate so that electric charges can be injected into or released from the floating gate resulting in the storage or erasure of data.
FIGS. 1A through 1C are schematic cross-sectional views showing some of the steps for fabricating a conventional flash memory device. First, as shown in FIG. 1A, a substrate 100 having a plurality of device isolation structures 102 thereon for defining active regions 104 and a tunneling dielectric layer on the active regions 104 is provided. A conductive layer 108 is formed over the substrate 100 to cover the device isolation structures 102 and the tunneling dielectric layer 106. Thereafter, a planarization operation is carried out to remove a portion of the conductive layer 108 and smooth out the top surface of the conductive layer 108.
As shown in FIG. 1B, a patterned photoresist layer 109 is formed over the conductive layer 108. The patterned photoresist layer 109 exposes a portion of the conductive layer 108 on the device isolation structure 102. Thereafter, using the patterned photoresist layer 109 as a mask, a portion of the conductive layer 108 is removed to form a plurality of trenches 107 in the conductive layer 108 above the device isolation structures 102. The conductive layer 108 retained after forming the trenches 107 becomes the floating gate 110.
After removing the patterned photoresist layer 109, an inter-gate dielectric layer 112 is formed over the substrate 100 to cover the floating gate 110 as shown in FIG. 1C. Finally, a control gate 114 is formed over the inter-gate dielectric layer 112.
In the aforementioned fabrication process, the floating gate 110 is formed using photolithographic and etching processes. However, photolithographic and etching processes involve steps such as de-moisturize heating, coating, photoresist deposition, soft baking, photo-exposure, post photo-exposure baking, chemical development, hard baking and etching. Hence, the process not only is time consuming but also incurs additional production cost.
In addition, the aforementioned process utilizes a chemical-mechanical polishing (CMP) operation to planarize the conductive layer 108. Without a reference polishing stop layer, the thickness of conductive layer 108 retained after each chemical-mechanical polishing operation will be different. In other words, there is no control over to the thickness of the floating gate 110.
On the other hand, a larger gate-coupling ratio (GCR) between the floating gate and the control gate requires a lower operating voltage. The methods of increasing the gate-coupling ratio include increasing the capacitance of the inter-gate dielectric layer or reducing the capacitance of the tunneling oxide layer. One method of increasing the capacitance of the inter-gate dielectric layer is to enlarge the included area between the control gate and the floating gate. Thus, minimizing the size of the trenches 107 is able to increase the included area between the floating gate and the control gate and thus increase the gate-coupling ratio between them. However, when the conductive layer 108 is patterned, size of the trenches 107 is constrained by the photolithographic and etching processes. In other words, it is difficult to decrease the size of each trench 107 further. In the absence of any other method for increasing the included area between the control gate and the floating gate, improving the performance of the memory device is difficult.